NXP Semiconductors /NeoM3 /IOCON /P5_3

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as P5_3

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (P5_3)FUNC0RESERVED 0 (INPUT_NOT_INVERTED_)INV 0RESERVED 0 (ENABLED)HS 0 (LOWDRIVE)HIDRIVE 0RESERVED

FUNC=P5_3, HIDRIVE=LOWDRIVE, HS=ENABLED, INV=INPUT_NOT_INVERTED_

Description

I/O configuration register for pin P5[3]

Fields

FUNC

Selects pin function for pin P5[3]

0 (P5_3): General purpose digital input/output pin.

4 (U4_RXD): Receiver input for USART4.

5 (I2C0_SCL): I2C0 clock input/output (this pin uses a specialized I2C pad that supports I2C Fast Mode Plus.

RESERVED

Reserved.

INV

Invert input

0 (INPUT_NOT_INVERTED_): Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).

1 (INPUT_INVERTED_HIGH): Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

RESERVED

Reserved.

HS

Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation.

0 (ENABLED): I2C 50ns glitch filter and slew rate control enabled.

1 (DISABLED): I2C 50ns glitch filter and slew rate control disabled.

HIDRIVE

Controls sink current capability of the pin, only for P5[2] and P5[3].

0 (LOWDRIVE): Output drive sink is 4 mA. This is sufficient for standard and fast mode I2C.

1 (HIGHDRIVE): Output drive sink is 20 mA. This is needed for Fast Mode Plus I2C. Refer to the appropriate specific device data sheet for details.

RESERVED

Reserved.

Links

()